FPGA on tplat

Verilog

Mon, 01 Jan 0001 00:00:00 +0000

Verilog#

Keywords#

wire#

wire keyword represents a physical wire in a circuit and is used to connect gates or modules.

wire is a type of net that describes digital signals connecting multiple hardware elements.

wire does not store its value but must be driven by a continuous assignment statement assign or by connecting it to the output of a gate or module.

Value of a wire can be read or assigned inside a module but never inside procedural code such as intial or always blocks.

1-bit MUX

Mon, 01 Jan 0001 00:00:00 +0000

1-bit MUX#

A multiplexer (MUX) is an electronic switch that conencts one of several inputs to the output based on a selection signal S. The truth table for a 1-bit MUX is shown in Table 1.

Table 1: Truth table of a 1-bit MUX.

X	Y	S	Z
0	xx	1	0
1	xx	1	1
xx	0	0	0
xx	1	0	1

As shown in Table 1, when the selector signal is 1, the output signal mirrors input signal X. Conversely, when the selector signal is 0 the output signal mirrors the input signal Y.

1-bit Full Addder

Mon, 01 Jan 0001 00:00:00 +0000

1-bit Full Addder#

A full adder is an adder with carry-in and carry-out ports. The truth table for a 1-bit full adder is shown in Table 1.

Table 1: Truth table for a 1-bit full adder.

X	Y	C_in	Z	C_out
0	0	0	0	0
0	1	0	1	0
1	0	0	1	0
1	1	0	0	1
0	0	1	1	0
0	1	1	0	1
1	0	1	0	1
1	1	1	1	1

As shown in Table 1, the output $Z$ is the binary addition of $X + Y + C_{in}$, and the output $C_{out}$ is the carry bit of the addition.

Hazards

Mon, 01 Jan 0001 00:00:00 +0000

Hazards#

The 1-bit multiplexer and 1-bit full adder exercises treat circuits as ideal, i.e., with instantaneous signal changes. However, transition times in digital circuits are non-zero. When designing asynchronous digital circuits, attention must be paid to the possible presence of hazards.

Note:

All combinational circuits are asynchronous.

Consider the previously defined 1-bit multiplexer.

Figure 1: Schematic description of 1-bit MUX.

Not all signal pathways corss the same number of gates, which means they will be affected by varying amounts of delay. This can introduce timing hazards.

Overflow Counter

Mon, 01 Jan 0001 00:00:00 +0000

Overflow Counter#

An overflow counter is a counter that can overflow back to zero when it fills up.

In the overflow counter subfolder, a 32-bit overflow counter is implemented for a Basys 3 FPGA board, part number: xc7a35tcpg236-1.

The counter has 3 inputs: (1) clk, (2) reset, and (3) enable with the output being a 16-bit bus entity called led. The counter has the following behaviour:

At every positive (i.e., rising) edge of the clk signal, the counter’s value increases by 1. This is achieved using a procedural block that will be edge-triggered by the clock. This is specified by the condition posedge clk.
For condition reset == 1, the counter’s value resets to 0. When reset == 0, the counter increments.
The counter increments when enabled (i.e., enable == 1) and stops incrementing when disbled (enable == 0).

The full procedural block describing this behaviour is given by:

Clock Division

Mon, 01 Jan 0001 00:00:00 +0000

Clock Division#

The overflow counter project uses a 100 MHz clock signal. In many cases, it is necessary to generate clock signals slower than 100 Hz. A very efficient way to do this is to perform clock division using an overflow counter.

Clock Division using an Overflow Counter#

The simplest way to generate a clock divided by a factor of $2^n$ is to output the (n-1)th bit of an overflow counter (n-1 because bus indexing starts at 0).

Seven Segment Display

Mon, 01 Jan 0001 00:00:00 +0000

Seven Segment Display#

The Basys 3 board features a four-digit common anode seven-segment LED display. Each of the four digits is comprised of seven segments, with an LED embedded in each segment. Segment LEDs can be individually illuminated. Any of the 128 (2^7) patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark.

Figure 1: Seven segment display.

The anodes of the seven LED segments are tied together to form one common anode circuit node. The common anode signals are available as four digit enable input signals (i.e., 1000 will enable the first anode, but not the other three). The cathode circuit connections are shared amongst the four digits. There are only eight cathode signals that are drivable from the FPGA chip, called CA, CB, …, CG and DP (decimal point), and there are connected to all four digits on the display.